The definitive technical guide for engineers designing 10-layer printed circuit boards — stackup configurations, impedance control, materials, DFM rules, and manufacturing specs all in one place.
A well-planned layer assignment is the foundation of every successful 10-layer PCB design. Below is the industry-standard stackup used for high-speed digital designs, with full material specifications.
| Layer | Function | Material | Thickness | Dk | Zo (Ω) | |
|---|---|---|---|---|---|---|
| L1 TOP | Signal | 1oz Cu | 35 µm | — | 50 Ω | |
| Prepreg 2116 — 0.1mm — Dk 4.4 | ||||||
| L2 GND | Ground Plane | 1oz Cu | 35 µm | — | — | |
| Core FR4 — 0.2mm — Dk 4.3 | ||||||
| L3 IN1 | Signal (H) | 0.5oz Cu | 18 µm | — | 50 Ω | |
| Prepreg 7628 — 0.2mm — Dk 4.5 | ||||||
| L4 IN2 | Signal (V) | 0.5oz Cu | 18 µm | — | 50 Ω | |
| Core FR4 — 0.36mm — Dk 4.3 | ||||||
| L5 PWR | Power Plane | 1oz Cu | 35 µm | — | — | |
| Prepreg 2116 — 0.1mm — Dk 4.4 | ||||||
| L6 GND | Ground Plane | 1oz Cu | 35 µm | — | — | |
| Core FR4 — 0.36mm — Dk 4.3 | ||||||
| L7 IN3 | Signal (H) | 0.5oz Cu | 18 µm | — | 50 Ω | |
| Prepreg 7628 — 0.2mm — Dk 4.5 | ||||||
| L8 IN4 | Signal (V) | 0.5oz Cu | 18 µm | — | 50 Ω | |
| Core FR4 — 0.2mm — Dk 4.3 | ||||||
| L9 GND | Ground Plane | 1oz Cu | 35 µm | — | — | |
| Prepreg 2116 — 0.1mm — Dk 4.4 | ||||||
| L10 BOT | Signal | 1oz Cu | 35 µm | — | 50 Ω | |
Material selection directly impacts signal integrity, thermal performance, and board cost. Here are the most common dielectric materials for 10-layer PCBs.
Meeting manufacturer tolerances from day one avoids costly respins. These figures represent standard production (STD) and advanced/HDI (ADV) capability limits.
| Parameter | STD | ADV / HDI |
|---|---|---|
| COPPER FEATURES | ||
| Minimum trace width | 0.1 mm | 0.075 mm |
| Minimum trace spacing | 0.1 mm | 0.075 mm |
| Outer copper weight | 1 oz (35 µm) | 0.5 – 3 oz |
| Inner copper weight | 0.5 oz (18 µm) | 0.5 – 2 oz |
| VIAS | ||
| Min via drill (PTH) | 0.2 mm | 0.1 mm (laser) |
| Min via pad diameter | 0.4 mm | 0.2 mm |
| Via aspect ratio (max) | 8:1 | 12:1 |
| Blind / buried vias | No | Yes (HDI) |
| BOARD PARAMETERS | ||
| Board thickness | 1.6 mm | 0.6 – 3.2 mm |
| Thickness tolerance | ±10% | ±8% |
| Impedance tolerance | ±10% | ±5% |
| Bow & twist (max) | 0.75% | 0.5% |
Estimate microstrip or stripline trace impedance for FR4 (Dk = 4.3)
Hard-won insights from years of high-speed multilayer design. Apply these rules from day one to save costly respins.
Every signal layer must have an adjacent ground or power plane for return current. In a 10-layer stackup, L1/L2, L3/L4, L7/L8, and L9/L10 should form signal+reference pairs. Violating this collapses impedance control and spikes EMI.
SIGNAL INTEGRITYRoute L3 horizontal, L4 vertical (and L7 horizontal, L8 vertical). This minimizes capacitive coupling between adjacent signal layers — critical for DDR, PCIe, and high-speed serial interfaces.
EMI REDUCTIONPlacing L5 (Power) and L6 (GND) with minimal separation (0.075–0.1 mm prepreg) creates distributed capacitance of ~200 pF/cm². This suppresses power-plane noise without extra decoupling caps.
POWER INTEGRITYGround via stitching every λ/20 along high-speed signal corridors closes the return path loop. Typical spacing for a 5 GHz trace is ≤ 3 mm between stitching vias along the trace edge.
RETURN PATHThrough-hole vias create stubs when a signal transitions layers. For traces above 5 GHz, back-drill unused via stubs or switch to blind/buried vias to eliminate resonance notches in the insertion loss.
HIGH-SPEEDNever route a high-speed signal over a split in the reference plane. If a signal must change layers, place a stitching capacitor (100 nF) near the via, connecting the two reference planes, to keep the return current path unbroken.
SIGNAL INTEGRITYTo avoid crosstalk, maintain edge-to-edge spacing of 3× the trace width (3W) for clocks, differential pairs, and RF signals. The 20H rule for plane edges (pull back power planes by 20× dielectric height) suppresses edge radiation.
CROSSTALKFor LVDS, PCIe, USB 3.x, and HDMI differential pairs, intra-pair skew must be under 5 ps/inch. Length-match both traces within 0.1 mm, keep pairs together, and never split them across different reference plane splits.
DIFFERENTIAL PAIRSUnderstanding the fabrication sequence helps you design for manufacturability and avoid common DFM failures that increase cost and lead time.
| Finish | Full Name | Thickness | Shelf Life | Best For | Cost |
|---|---|---|---|---|---|
| HASL | Hot Air Solder Level | 1 – 40 µm | 12 months | General purpose, THT | Low |
| ENIG | Electroless Nickel Immersion Gold | Ni 3–6µm / Au 0.05–0.1µm | 12 months | Fine pitch SMD, BGA | Medium |
| OSP | Organic Solderability Preservative | 0.2 – 0.5 µm | 6 months | High-volume SMT | Low |
| ENEPIG | Ni/Pd/Au | Ni 3-6 / Pd 0.1-0.15 / Au 0.05µm | 12 months | Wire bond, gold finger | High |
| Immersion Ag | Immersion Silver | 0.1 – 0.3 µm | 6 months | RF, high-speed | Medium |
Indicative pricing for standard FR4, 1.6mm, ENIG, 1oz outer / 0.5oz inner, 50Ω controlled impedance. Prices vary by manufacturer and specifications.
| Qty (pcs) | 100×100mm | 200×200mm | 300×300mm | Lead Time | Notes |
|---|---|---|---|---|---|
| 5 | $180 – $260 | $320 – $480 | $560 – $820 | 7–10d | Prototype / engineering samples |
| 10 | $240 – $360 | $450 – $650 | $780 – $1,100 | 7–10d | Small prototype run |
| 50 | $480 – $680 | $820 – $1,200 | $1,400 – $2,000 | 8–12d | Pre-production pilot |
| 100 | $680 – $980 | $1,200 – $1,800 | $2,200 – $3,200 | 10–14d | Low-volume production |
| 500 | $2,400 – $3,600 | $4,800 – $7,200 | $8,000 – $12,000 | 12–18d | Medium production volume |
| 1000+ | Contact us | Contact us | Contact us | 14–21d | Volume pricing with NRE |
10-layer PCBs strike the ideal balance between density, signal integrity, and cost — making them the dominant choice across advanced electronics sectors.
Use this interactive checklist before sending your Gerbers to the fab. Track your readiness with the live progress indicator.
Answers to the most common questions from engineers designing their first (or fifth) 10-layer board.
SIG/GND/SIG/SIG/PWR/GND/SIG/SIG/GND/SIG handles most complex digital designs efficiently.
1.6 mm ± 10%. This is the most common spec and fits standard connectors and mechanical assemblies. Thinner (1.0 mm, 0.8 mm) and thicker (2.0 mm, 2.4 mm) options exist for specialized mechanical requirements. Note that aspect ratio for via drilling (board thickness / drill diameter) must stay below 8:1 for standard fab, or 12:1 for advanced HDI fab — this constrains how thin you can go while using 0.2 mm drill holes.
0.12 mm gives 50Ω. The manufacturer validates with TDR (Time Domain Reflectometry) coupons fabricated on the same panel. Specify your target impedance and ±% tolerance on the fab drawing — standard tolerance is ±10%, advanced is ±5%. Use our calculator above to estimate trace widths for your specific stackup parameters.
10× copper layer files (one per layer), drill files (Excellon format, separate for PTH and NPTH), board outline (in a separate .GKO or mechanical layer), soldermask (top and bottom), silkscreen (top and bottom), and a stackup specification document with layer order, material, thickness, Dk, and impedance requirements. For IPC-2581 or ODB++ formats, a single file covers all layers. Always include a fabrication drawing PDF with board dimensions, tolerances, finish, IPC class, and any special notes.
Get instant DFM feedback, competitive pricing, and expert stackup review from PCBSync's engineering team. Upload your Gerbers and receive a quote in minutes.